Integrated circuit (IC) manufacturers increasingly face difficulties with scaling and insulation between components with ever decreasing feature sizes. Even though packing transistors closer is important to the concept of increasing IC speed and decreasing size, they must still be electrically separated from each other. One method of keeping transistors separate from each other is known as trench isolation. Trench isolation is the practice of creating trenches in the substrate in order to separate electrical components on the chip. The trenches are typically filled with an insulator that will prevent cross-talk between transistors.
Shallow trench isolation (STI), which is becoming quite prevalent in modem IC design, uses trenches that are substantially narrower than field isolation elements created by older isolation technology, such as LOCal Oxidation of Silicon (LOCOS). The size can vary, but a trench less than one half of a micron wide has become quite common. STI also offers smaller channel width encroachment and better planarity than technologies used in earlier IC generations. Good insulating trenches are important for devices such as dynamic random access memory (DRAM), which uses trenches to separate transistors of individual memory cells.
During the deposition process and subsequent steps, however, the trench walls can be damaged. A silicon nitride liner, which has substantial stress-relieving capabilities for the sidewalls of the trench, may be added before trench fill. Such liners are often used for high density ICs, such as DRAM chips, to protect bulk silicon during subsequent process steps.
In order to provide good isolation properties, the trench is then typically filled with an insulator such as a form of silicon oxide. The oxide can be deposited in a number of methods, such as CVD, sputtering, or a spin-on deposition process. Spin-on insulators are becoming more prevalent, because they fill low points first and thus fill trenches more evenly. Additionally, spin-on deposition (SOD) dielectric materials, which often form silicon oxide after being reacted, carry less risk of voids in the resulting insulating material than other deposition processes. SOD precursors are deposited as a liquid, and then reacted to form silicon oxide using a high temperature oxidation process.
However, the use of SOD insulators in the trench can also raise issues upon the conversion from liquid precursor to its final insulating form. Three interrelated problems arise upon the conversion from precursor to insulation material: poor rebonding, volume shrinkage, and wet etch rate gradients. Upon densification, the insulation material bonds to the walls of the trench, but if the bonds are not very strong, the insulator will be easily etched near the side of the trench during subsequent etch processes. These bonds and the general crystal structure can be weakened due to the volume shrinkage during densification of the SOD material pulling the SOD material away from the sidewalls. This can change the angles in the crystal structure, resulting in easily broken bonds and high etch rates.
During fabrication of a semiconductor device, the trench is typically exposed to several etching steps. If the trench fill material has different etch rates in different regions, it will be hard to control the etch processes to avoid removing the trench fill. This problem is particularly true at the walls of the trench, where the fill material is less dense due to volume shrinkage. The etch process can create voids along the walls of the trench, reducing the effectiveness of the trench structure as an isolating device.
Problems relating to the formation of the densified SOD material are common and can cause significant problems for IC designers. Accordingly, better methods of SOD integration are needed for trenches.